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Abstract: ADV202 is a JPEG2000 codec chip introduced by AD. The chip uses patented space ultra-efficient regression filtering (SURF) technology with low power consumption and cost. The main features and working principle of ADV202 are introduced in this paper, and several typical application circuits of ADV202 are given.Keywords: JPEG2000 ADV202 SURF codec
ADV202 is a new single-chip JPEG2000 (ISO/IEC15444-1 image compression standard) codec chip from AD. It is a rare real-time compression and decompression standard (SD) video signal and high definition (HDTV) on the market. ) The chip of the video signal function. The chip comes with a flexible interface for a wide range of video and still image formats.
1 Main features
Fully single JPEG2000 compression and decompression solution for video and still images;
· Patented Space Super Efficiency Regression Filtering (SURF) technology enables low-power and low-cost wavelet compression;
· Supports up to 6 levels of 9/7 and 5/3 wavelet transforms;
Programmable block/image size, up to 2048 pixels in 3-component 4:2:2 interlaced scanning, and 4096 pixels in single-component mode;
· Maximum tile/image height: 4096 pixels;
· The video interface can directly support ITU.R-BT656, SMPTE125M PAL/NTSC, SMPTE274M, SMPTE293M (525p), ITU.R-BT1358 (625p), and the maximum input speed of irreversible mode is 65Msps, and the maximum input speed of reversible mode is 40Msps. Any video format;
· Two or more ADV202s can be combined with full frame SMPTE274M HDTV (1080i) or SMPTE296M (720p);
Flexible asynchronous SRAM type host interface can seamlessly connect to most 16/32-bit microcontrollers and ASICs;
The 115MHz product is available in a 12mm x 12mm 121-pin CSPBGA package and the 150MHz product is available in a 13mm x 13mm 144-pin CSPBGA package.
Depending on the specific application requirements, the ADV202 provides different standards supported by JPEG2000 compression, providing raw coding modules and feature data output, while JPEG2000 code stream generation and other compression processes such as bit rate control are fully implemented by the host software. control. In addition, it can also produce complete, fully compatible JPEG2000 stream (j2c) and jp2, jpx and mj2 (motion JPEG2000) enhanced formats.
2 Working principle
The internal functional block diagram of the ADV202 is shown in the figure. The chip is mainly composed of a pixel interface, a wavelet transform engine, an entropy codec, an embedded processor, a memory system, and an internal DMA engine. The input image and pixel data are input to the pixel interface, and the sampled values ​​are transmitted to the wavelet transform engine through interlaced scanning. In the wavelet engine, each tile or frame will be decomposed into many subbands by a 5/3 or 9/7 filter. The generated wavelet coefficients are written to the internal registers. The entropy codec encodes image data into data conforming to the JPEG2000 standard. The internal DMA engine provides high bandwidth transfers between memories and high performance transfers between modules and memories.
2.1 Wavelet Transform Engine
Because the ADV202 contains a dedicated wavelet transform processor based on the patented SURF technology of AD. Therefore, it can perform up to 6 levels of wavelet decomposition on a tile. In the coding mode, the wavelet transform processor will wavelet transform and quantize the uncompressed sample values, and then write the wavelet coefficients of all frequency subbands into the internal memory. These sub-bands are further decomposed into coded blocks of user-defined size. When wavelet coefficients are written to the internal memory, the wavelet coefficients are typically organized by a wavelet transform processor. In the decoding mode, the wavelet coefficients are read from the internal memory to regenerate the sample values ​​when uncompressed.
2.2 Entropy codec
The entropy codec is used to perform background modeling and arithmetic coding on the coded blocks of wavelet coefficients, and to calculate the distortion necessary for optimal rate and distortion performance during compression. Since the entropy encoding process has the highest computational requirements in the JPEG2000 compression project, the ADV202 internally provides three dedicated hardware entropy codecs.
2.3 embedded processor
A 32-bit RISC processor is embedded in the ADV202 to configure, control, and manage other dedicated hardware blocks and to decompose and generate JPEG2000 video streams. The RISC processor has a ROM and RAM corresponding to each program and data memory, interrupt controller, standard bus interface, and timer counter.
2.4 Memory System
The main functions of the memory system are to manage the coefficient data of the wavelet transform, temporarily store the feature data of the coded block, and provide temporary storage space for the JPEG2000 code stream. It can also be used as a program and data memory for embedded processors.
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   2.5 Internal DMA Engine
The internal DMA engine provides high bandwidth transfer between memories and high performance transfers between modules and memory. This is important for the decomposition of the code stream and the generation of high-rate data.
2.6 Configurable FIFO Module
The internal FIFO is used to provide storage space for pixel data, encoded streams, feature data, or other auxiliary data. It can be accessed directly by the host interface during the normal address read/write cycle, or by the external host DMA using the DREQ/DACK protocol or a dedicated hardware handshake mechanism. Each FIFO has a programmable threshold for generating an interrupt.
2.7 Video and Host Interface
There are several modes that can be used to configure the interface of the ADV202. Designers can use both the VDATA bus and the HDATA bus, or they can use the HDATA bus alone.
(1) Video interface (VDATA bus)
The video interface is mainly used in the case where uncompressed pixel data and compressed data are separated. For example, the uncompressed data is input by the VDATA bus, and the compressed data and the like are output through the HDATA bus.
The video interface supports 8, 10, 12-bit single or multiple formats, and also supports dual-channel 8, 10, 12-bit format video and still image data. It also supports YcrCb format digital video and dual channel input mode in single channel input mode. Digital video signals in Y and CrCb format, but YcrCb data must be in 4:2:2 format. The VDATA bus can support the input and output of video data in multiple formats. Table 1 lists the video input and output formats that it can support.
Table 1 Video input and output mode
| Video mode | Description |
| EAV/SAV mode | Video containing EAV/SAV encoding, YCrCb interlaced on a single bus |
| HVF mode | H, V, F independent video signals, YCrCb interlaced on a single bus |
| Dual channel mode | Contains EAV/SAV encoded video, Y and YCrCb on separate buses |
| Original video mode | For still images and non-standard video |
| HDTV mode | For video data above 27MHz clock signal |
(2) Host interface (HDATA bus)
The ADV202 can be directly connected to most host processors and ASICs via asynchronous SRAM, DMA access or code streaming. The ADV202 is available with 16-bit and 32-bit control buses and 8, 16, and 32-bit data transfer buses. The host interface is used to configure, control, and transfer compressed data streams, and in some formats can also be used as a transport for uncompressed data streams. The host interface is shared by four concurrent data streams and control and status communications. The pixel data input to the host interface supports 8, 10, 12, 14 and 16-bit raw pixel data. It can be used both as an input and output for still images and as an output for compressed video data.
3 Typical applications
3.1 Multi-chip coding mode
Due to the limitations of the input data rate, a 1080i video signal application system requires at least two ADVs 202 to encode or decode a video signal with a full resolution of 1080i. Figure 2 shows its encoding mode. Y data and CbCr data are input to the ADV 202 through different buses, where AD202_1 processes the luminance data of the 1080i video signal, and ADV202_2 is used to process the chrominance data of the 1080i video signal. In order to synchronize the corresponding output data in this application mode, the input data must be in the EAV/SAV encoding format. This mode is typically applied to the video output of the ADV202 directly to a receiving device that requires synchronization of luminance and chrominance data.
Multi-slice mode can also be applied to the decoding mode in master/slave or slave/slave configuration. In the coding mode, the ADV202 is usually used as a slave device. In order to make the acquired 1080i video signal have better characteristics (such as lossless compression), it is recommended to use three or more ADV202 to process the signal.
3.2 HPII (Host Interface - Pixel Interface) Decoding Mode
The ADV202 allows input and output video and still images over the HDATA bus without the dedicated video interface provided by the VDATA bus. This mode is called HIPI mode.
Figure 3 shows the circuit connection of the ADV202 for HIPI decoding mode. The pixel data is output by HDATA1[31:1]. DMA channel 1 is used to input compressed data, while DMA channel 0 is used to write pixel data into the pixel FIFO. DREQ0/DACK0 is used to control the read and write process of channel 0, while DREQ1/DACK1 is used to control the read and write process of channel 1.
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