At the 2011 Technology Symposium held in California, USA, the company disclosed more details on the 18-inch wafer manufacturing plan. According to industry news, TSMC is advancing at full speed into the 18-inch wafer technology field. Its main purpose is to reduce the manufacturing cost and try to take the lead by competitors such as Globalfoundries, Samsung, and UMC.
There is another motivation behind TSMC's advancement into the 18-inch wafer technology area. According to Shang-Yi Chiang, senior vice president of R&D at the company, once the company enters the 18-inch wafer era, the number of engineers required by the company will also decrease. When he was interviewed by EETimes, he said that TSMC entered the 18-inch wafer manufacturing process in a transitional period of about ten years, and that the number of engineers needed would be 7,000 less than it is now.
Jiang Shangyi pointed out that there are two considerations for TSMC's advancement into manufacturing of 18-inch wafers: First, the company believes that it will be increasingly difficult to recruit “good engineers†over time; secondly, TSMC only needs a few 18-inch wafers in the end. Fabs can meet customer needs in the future. Compared with the 12-inch wafer fab, the overall productivity of the new-generation wafer size is expected to increase by 1.8 times. With fewer fabs, fewer engineers are needed.
On the other hand, TSMC is also expected to increase R&D and capital expenditures, especially as the company continues to work to shorten the process technology learning curve. It is estimated that the operating cost of an 18-inch wafer fab will be approximately US$10 billion and the cost of related process equipment will also soar.
Jiang Shangyi said that TSMC's 18-inch wafer fabrication will start at the 20-nanometer process node; the company initially planned to build an 18-inch wafer trial production line at Fab 12 fab in Hsinchu, using a 20-nanometer manufacturing process. Between 2013 and 2014. TSMC’s 12-inch wafer fab will also enter the 20-nanometer process; Jiang Shangyi said that the company’s initial production of 20-nanometer process will in fact be based on 12-inch fabs.
Next, TSMC plans to build its first 18-inch wafer fab, Fab15, in Taichung. The volume production schedule is scheduled to be between 2015 and 2016. In the start-up phase, the 18-inch wafer fab will use a 20-nanometer process and then enter the 14-nanometer node; at the 14-nanometer node, TSMC intends to convert the transistor structure.
At 20nm and beyond, TSMC will continue to use conventional bulk CMOS-based planar transistors, but starting at the 14nm node, the company will move from bulk CMOS to FinFET structures. In other words, in the future, Taiwan Semiconductor Manufacturing Co. will mass-produce 14-nm FinFETs on Fab 15.
There is another motivation behind TSMC's advancement into the 18-inch wafer technology area. According to Shang-Yi Chiang, senior vice president of R&D at the company, once the company enters the 18-inch wafer era, the number of engineers required by the company will also decrease. When he was interviewed by EETimes, he said that TSMC entered the 18-inch wafer manufacturing process in a transitional period of about ten years, and that the number of engineers needed would be 7,000 less than it is now.
Jiang Shangyi pointed out that there are two considerations for TSMC's advancement into manufacturing of 18-inch wafers: First, the company believes that it will be increasingly difficult to recruit “good engineers†over time; secondly, TSMC only needs a few 18-inch wafers in the end. Fabs can meet customer needs in the future. Compared with the 12-inch wafer fab, the overall productivity of the new-generation wafer size is expected to increase by 1.8 times. With fewer fabs, fewer engineers are needed.
On the other hand, TSMC is also expected to increase R&D and capital expenditures, especially as the company continues to work to shorten the process technology learning curve. It is estimated that the operating cost of an 18-inch wafer fab will be approximately US$10 billion and the cost of related process equipment will also soar.
Jiang Shangyi said that TSMC's 18-inch wafer fabrication will start at the 20-nanometer process node; the company initially planned to build an 18-inch wafer trial production line at Fab 12 fab in Hsinchu, using a 20-nanometer manufacturing process. Between 2013 and 2014. TSMC’s 12-inch wafer fab will also enter the 20-nanometer process; Jiang Shangyi said that the company’s initial production of 20-nanometer process will in fact be based on 12-inch fabs.
Next, TSMC plans to build its first 18-inch wafer fab, Fab15, in Taichung. The volume production schedule is scheduled to be between 2015 and 2016. In the start-up phase, the 18-inch wafer fab will use a 20-nanometer process and then enter the 14-nanometer node; at the 14-nanometer node, TSMC intends to convert the transistor structure.
At 20nm and beyond, TSMC will continue to use conventional bulk CMOS-based planar transistors, but starting at the 14nm node, the company will move from bulk CMOS to FinFET structures. In other words, in the future, Taiwan Semiconductor Manufacturing Co. will mass-produce 14-nm FinFETs on Fab 15.
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