Integrating silicon-validated audio IP optimized for specific audio functions into today's multimedia system chips will help reduce power consumption, reduce volume, and reduce costs. But as the next-generation design moves toward 28nm process technology, new challenges will emerge. The audio design in the audio codec includes many analog circuits. It will not be "small" with the development of process technology, so it does not follow the traditional Moore's law.
28nm process technology increases wafer costs, and system architects and SoC designers must consider how this affects the economics of integrating audio codecs into SoCs. Synopsys tested several mobile multimedia devices currently on the market and found that most smartphones and tablets currently support audio codecs developed using the 28nm process.
This article introduces the test results and discusses the commercial and technical challenges faced by integrating audio functions into a 28nm mobile multimedia SoC, and explains how to overcome these challenges. This article also explains some key design considerations, including scaling limits, power supply voltage requirements, and system partitioning options.
Audio codec basics: For clarity and ease of discussion, use an audio codec described in Figure 1 below. Audio editing? ? The encoder includes microphone and line input, signal streaming and mixing, amplifier module, multi-channel ADC and DAC. It also includes various output drivers, including line output, headphone and speaker drivers, and a small digital signal processing module containing decimation / interpolation filters and a standard I2S digital audio interface.
Figure 1: A block diagram of a typical audio codec.
28nm process technology cost considerations: In 28nm process technology, wafer cost is much higher than 65nm technology. For digital circuits that follow Moore's Law, higher wafer costs can be compensated by increased gate density, possible integration into more functions, and higher performance to prove their value for money.
Analog circuits, such as audio codecs that widely use I / O devices, do not decrease with shrinking process nodes in the same way as digital circuits that mainly use core devices. Unless the wafer area can be reduced by 25-30%, higher wafer costs will significantly increase the overall silicon cost of audio technology.
For example, to maintain the same silicon cost, a 2.5mm2 audio codec implemented with 65nm technology needs to be reduced to 1.9mm2 when implemented with a 28nm process. Figure 2 below shows the cost forecast for each 12-inch wafer by 2013 (based on the 65nm process). The production cost of 28nm wafers is expected to be nearly 40% higher than that of 65nm wafers.
Figure 2: In 2013, the wafer production cost of different processes was based on 65nm (source: Selantek).
Because the circuit performance of the 28nm technology has not improved significantly compared to the audio circuit with the same function implemented in 65nm technology, the cost of silicon chips is one of the key factors in deciding whether to integrate audio functions. Figure 3 below shows the area required by different process technologies to maintain the same silicon cost compared to the 2.5mm2 audio codec implemented with the 65nm process.
Figure 3: Compared with the 2.5mm2 audio codec implemented with 65nm process, in order to maintain the same silicon cost, different process technology to achieve the required area.
The following sections of this article will discuss the key technical challenges of integrating audio codecs at the 28nm process geometry. Each challenge can be solved by improving the circuit or system to provide the SoC with the most optimized power consumption and cost.
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