The H.264 codec IP (including AL-H264E-4KI422-HW encoder and AL-H264D-4KI422-HW decoder) developed by Atria Logic is ported to Xilinx Zynq Z-7045 SoC, which can realize UHD 4K @ 60fps video The operation of the stream is shown in the following figure:
ArTIa Logic company developed H.264 codec IP design block diagram
The AL-H264E-4KI422-HW encoding IP core designed by ArTIa Logic is hardware-based, with rich features, low latency, high quality, and H.264 (AVC) UHD Hi422 intra-frame encoding. The AL-H264E-4KI422-HW encoder is paired with the AL-H264D-4KI422-HW low-latency decoder.
The IP core contains the following features:
Comprehensive modular design, support user customization and expansion
Support intra-frame H.264 and Hi422 5.1 encoding and decoding
Integrated HDMI2.0 receiving and transmitting subsystem
Support 8/10 bit codec
Support RGB, YUV 4: 2: 2/4: 4: 4
Low latency ~ 0.3 seconds
Supports variable bit rate (VBR) and constant bit rate (CBR) modes
Video quality 0.99% SSIM, or 50dB PSNR or higher
Video processing subsystem for pre / post processing, including color space conversion, video scaling, and density subsampling
Support Gbps Ethernet data stream output
We need to design a solution to evaluate our UHD encoding and decoding IP core to meet the performance needs of 4K @ 60fps, then we need a flexible and powerful platform. In the end, we chose the Xilinx ZC706 evaluation kit, which is based on the Zynq Z-7045 SoC, for the following reasons:
There is a ready-made FMC expansion board that provides 4K HDMI video interface: TB-FMC-HDMI 4K 2.0 version daughter card
Zynq Z-7045 SoC's rich programmable logic resources can adapt to encoder and decoder IP logic and meet strict timing requirements to meet performance requirements
The Zynq SoC processor system integrates a dual-core ARM Cortex-A9 MPCore processor, which gives us the ability to modify application driver software and custom designs, such as GUI interfaces for application design
H.264 encoder supports H.264 Hi422 format configuration, 5.1 standard (3840x2160p30) unique encoding within the frame. Supports 10-bit video streaming. This means that grayscale and color degradation will not occur from the video strip. Supporting YUV4: 2: 2 video streaming means better color division—especially for red—which makes the image clearer. Video quality is very important for medical imaging occasions.
Atria Logic UHD H.264 encoder IP block diagram
Intra-frame coding allows the H.264 encoder to achieve frame rate delay, and the macro-module pipeline architecture design further reduces the delay: about 0.3 milliseconds. The pipeline design supports eight pixels per clock to achieve real-time 4K @ 60fps video encoding.
The H.264 encoder developed by Atria Logic uses only 78% of the programmable logic and DSP resources of the Zynq Z-7045 SoC and 55% of the available RAM, leaving enough space for other necessary circuits.
H.264 decoder supports H.264 Hi422 format configuration, 5.1 standard (3840x2160p30) unique encoding within the frame. Like the encoder, it supports 10-bit video stream encoding, that is, grayscale or color degradation will not occur from the video strip. The decoder also supports YUV 4: 2: 2 video format, supports intra-frame decoding, and uses a pipeline architecture to achieve the decoder's frame rate delay.
Atria Logic UHD H.264 decoder IP block diagram
Low latency is very important for any closed-loop human / machine application. When the AL-H264E-4KI422-HW encoder and the AL-H264D-4KI422-HW low-latency decoder are connected through an IP network, the glass delay time is approximately 0.6 milliseconds (excluding transmission time). This is approximately the delay time of two frames.
The implementation of the Atria Logic H.264 decoder occupies only 68% of the programmable logic resources of the Zynq Z-7045 SoC, 35% of the DSP resources, and 45% of the RAM, leaving enough space for other necessary circuits.
The HDMI subsystem includes two main modules: Xilinx LogicCore HDMI TX and RX subsystem, as shown below:
The HDMI transceiver (GTX) module sends and receives serial HDMI TX and RX transmitted data and converts it before the serial data stream and on-chip parallel data stream. The transceiver module realizes the mutual conversion between parallel data and serial data using Zynq SoC high-speed GT transceiver as the HDMI PHY physical layer interface.
The TX subsystem includes a transmission module, AXI Video conversion, video timing control, and optional HDCP module. The Axi Video data stream channel transmits two to four pixels per clock to the HDMI TX subsystem, and supports 8, 10, and 12-bit data encoding. This data stream conforms to the video transmission protocol defined in the AXI Design Reference Manual (UG761). The video conversion module converts the input AXI-Stream to a local video format. The video timing controller is used to generate local video timing. Audio AXI Stream transmits multi-channel uncompressed audio data to the HDMI TX subsystem. The ARM Cortex-A9 processor of Zynq Z-7045 SoC controls the transmission module of the HDMI TX subsystem through the CPU interface.
The HDMI RX subsystem includes three AXI protocol interfaces. The video conversion bridge converts the captured local video into an AXI Stream data stream, and outputs these video data through the AXI Video interface, which conforms to the protocol specifications defined in the AXI Design Reference Manual (UG761). The video timing controller measures the video timing, and the received audio is sent out through the AXI Stream audio interface. The CPU interface implements control and status data communication with peripheral devices.
The HDCP module is optional and is not included in the standard IP core configuration.
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