New MP3 decoder chip VS1001K and its application

Abstract: VS1001K is a new MP3 decoder chip produced by VLSI SoluTIon of Finland. The chip contains high-quality stereo digital-to-analog converter (DAC) and headphone drive circuit, supporting PCM data input. It also has the advantages of small size, low power consumption, simple interface and cheap price. The article introduces the pin arrangement, internal structure and main features of VS1001K. At the same time, the functions and addresses of the registers in the SCI control interface of the VS1001K and the operation method of the SDI data interface are mainly introduced. Finally, the application circuit of VS1001K is given.

1 Introduction

At present, the MP3 audio data compression method used by INTERNET and portable players has become a recognized industry standard. This method quickly became popular all over the world due to its high compression ratio and good sound quality. But in fact, the core of many MP3 players is a MP3 audio decoding chip. VS1001K is a new MP3 decoder chip launched by Finland VLSI Solution. The chip contains high-quality stereo digital-to-analog converter (DAC) and headphone driver circuit, it supports PCM data input, and has the advantages of small size, low power consumption, simple interface, cheap price and so on. Therefore, it is expected to become the chip of choice for the new MP3 decoder.

2 Functional structure of VS100K

2.1 Pin function of VS100K

VS1001K has two package types: 28-pin SOIC dual-row and 49-pin BGA ball grid array. Figure 1 shows the pin layout of the 28-pin SOIC package. The specific function description of each pin is listed in Table 1.

Table 1 VS1001K pin functions

Table 2 SCI register functions

2.2 The internal structure of VS100K

The VS100K decoder chip integrates the VS DSP processor, and it also integrates stereo audio DAC, stereo headphone amplifier driver, and program ROM and program RAM. In addition, VS100K also has a serial data interface and control interface. Figure 2 is a block diagram of the internal structure of VS100K.

3 Working principle of VS100K

VS1001K mainly receives the external microprocessor to control commands and MP3 data through two serial interfaces SCI and SDI. Among them, SCI is used to receive control commands sent by external microprocessors, and SDI is used to receive MP3 data sent by external microprocessors.

3.1 SCI control interface

The control of VS100K is mainly achieved by operating 15 16-bit registers in SCI. Table 2 lists the names, addresses, types and functions of 15 16-bit registers of SCI. In fact, the main operation of the VS100K is done through the MODE register. Table 3 gives a description of the operating functions of the MODE register.

Table 3 MODE register operation method

The communication protocol between SCI and external microprocessor includes instruction byte, address byte and 16-bit word. Among them, the instruction byte takes 0X03 as a read register and 0X02 as a write register; the main purpose of the address byte is to determine the address of the address register, and its range is 0X00 ~ 0X0E. The 16-bit word is used to point to the value written or read from the specified register. Figure 3 shows the timing of the read and write operations of the SCI register.

3.2 SDI data interface

When the external microprocessor transmits MP3 data to the VS100K through the SDI interface, under different settings of the MODE register, the SDI can work in both master and slave modes.

When SDI works in master mode, its DClk signal is generated internally by VS100K (specifically, 512kHz or 1024kHz is determined by the SM IBCLK bit in the MODE register), and when SDI works in slave mode, DClk is input externally.

SDI usually carries on the data transmission in the unit of byte, and input the SATA data signal on the rising or falling edge of the DCLK (specifically determined by the SM_DACT bit in the MODE register). Whether the high bit is first or the low bit is first used in data transfer is determined by the SM DAC bit of the MODE register. SDI uses BSYNC signals to ensure that there is no misalignment during data transmission.

Figure 3, Figure 4

When SDI receives data in slave mode, if there is enough space in the on-chip FIFO, VS1001K will issue a high-level DREQ data request signal to indicate that it can receive at least 32 bytes of MP3 data.

4 Application of VS100K

Fig. 4 is the application circuit that VS100K connects with external microprocessor through SDI and SCI interface. As can be seen from the figure, because the VS100K decoder has integrated a digital-to-analog converter and an audio drive circuit for headphones in its chip, its peripheral circuit is very simple. In fact, the circuit in Figure 4 has been optimized for the interface circuit between VS100K and the microprocessor.

Regarding the software programming of reading and writing SCI registers or transferring MP3 data to SDI, the software programming may be different for different external microprocessors. But neither is very complicated. Due to space limitations, this article will not repeat them.

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