IP core (IP Core)
There are many IP cores in Vivado that can be used directly, such as mathematical operations (multipliers, dividers, floating-point arithmetic, etc.), signal processing (FFT, DFT, DDS, etc.). The IP core is similar to the function library in programming (for example, the printf() function in C language), which can be called directly, which is very convenient and greatly speeds up the development.
Three types of IP cores
The IP core has three different forms of existence: the HDL language form, the netlist form, and the layout form. Corresponding to the three types of IP cores we often say: soft core, solid core and hard core.
What is a soft core?
The IP soft core is usually submitted to the user in the form of HDL text. It is RTL-level design optimization and functional verification, but it does not contain any specific physical information. According to this, the user can synthesize the correct gate-level design netlist, and can carry out the subsequent structural design, which has great flexibility, and can be easily integrated with other external logic circuits by means of the EDA synthesis tool, according to each Different semiconductor processes are designed to have different performance devices. The soft IP core is also called a virtual component (VC-Virtual Component).
What is a hard core?
The IP hard core is based on the physical design of the semiconductor process. It has a fixed topological layout and specific process, and has been verified by the process to have guaranteed performance. The form that is provided to the user is a circuit physical structure mask layout and a full set of process files, which is a complete set of technologies that can be used.
What is a solid core?
The design level of IP solid core is between soft core and hard core. In addition to completing all the design of soft core, it also completes the design steps of gate level circuit synthesis and timing simulation. It is generally provided to the user in the form of a gate-level circuit netlist.
If all the things Vivado HLS is done, what else does Vivado do? Click RTL export to export the generated RTL-level VHDL/Verilog code in the form of Vivado project or IP core for further processing.
File type in vivado:
The .dcp file mainly includes information about PhysicalConstraints, Device Constraints, Netlists, and device.
The .dcp file is a collection of netlist files and constraint files in ise, but is collected in a file in vivado.
.xdc file, this is the constraint file of vivado. The constraint file of vivado and the constraint file of ise are very different compared with .ucf or .pcf. The constraint file in .xdc is actually a series of tcl statements, so for vivado The constraint file can be placed in the project as a source file, called in the synthesis and place and route; it can also be entered in the tcl console and executed immediately.
.xci file, this is a custom ip generated file, which contains all the information of the customized ip core, you can use this file to generate the required ip core, the role is similar to the .dcp file. There is also a .dcp file in the ip core.
The .rpt file, which is a report file output at the end of each process, is used to record some information in each process. Compared with the multiple output file formats in ise, this unified format is obviously better.
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